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・ Caproni Bergamaschi PL.3
・ Caproni Ca.1
・ Capricieuse
・ Capricious
・ Capricious (cheese)
・ Capricious Summer
・ Capricode
・ Capricola
・ Capricon
・ Capricorn
・ Capricorn (A Brand New Name)
・ Capricorn (astrology)
・ Capricorn (comics)
・ Capricorn (Jay Chou album)
・ Capricorn (manga)
Capricorn (microprocessor)
・ Capricorn (Mike Tramp album)
・ Capricorn and Bunker Group
・ Capricorn Assemblage
・ Capricorn Caves
・ Capricorn Climber
・ Capricorn Coast
・ Capricorn Coast Hospital
・ Capricorn Coast National Park
・ Capricorn Concerto
・ Capricorn Cougars FC
・ Capricorn District Municipality
・ Capricorn FM
・ Capricorn Highway
・ Capricorn leaf-eared mouse


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Capricorn (microprocessor) : ウィキペディア英語版
Capricorn (microprocessor)
The Capricorn family of microprocessors was developed by Hewlett-Packard in the late 1970s for the HP series 80 scientific microcomputers. Capricorn was first used in the HP-85 desktop BASIC computer, introduced in January 1980. Steve Wozniak was inspired to build the Apple to be a computer like the HP 9830, and in 1976 he offered HP rights to the Apple computer. He was turned down and was given a release. When the calculator division started an 8 bit computer project called Capricorn, he left for Apple when he wasn't allowed to work on that project.〔(Byte Interview with Steve Wozniak )〕〔(Old Computers HP-85 )〕
== Architecture ==

The Capricorn is a microprogrammed CPU containing 64 eight-bit registers, an eight-bit arithmetic logic unit (ALU), a shifter and control logic. One register pair is defined as the program counter, another pair as the stack pointer, and one more pair as an index pointer for internal operations. There is no dedicated accumulator — any general register can be used for ALU results because the register file is designed to allow two read and one write operations at the same time. Any pair of registers can be used as a 16-bit index register.
The ALU can work either in binary or binary-coded decimal (BCD) mode. Variable-length instructions let the programmer treat data in the upper 32 registers as entities between one and eight bytes in length — for example, two eight-byte values (e.g. mantissa of a floating-point number) can be added using a single instruction. This feature reduces the number of loops that need to be programmed.

The CPU has an interrupt mechanism with up to 127 vectors. For direct memory access, the CPU can be halted by an external device.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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